Workshop on Portability Among HPC Architectures for Scientific Applications

Workshop on Portability Among HPC Architectures for Scientific Applications



Sunday 15 November 2015
9:00 am – 12:30 pm
Hilton Salon G, 6th floor [NOTE CHANGE]


This workshop will explore how the large-scale scientific HPC developer community can and should engineer our applications for portability across the distinct HPC architectures of today, the next generation of large systems, and on toward exascale. How should HPC centers advise computational scientists to develop codes that scale well, have good aggregate and single-node performance, yet are as source-code portable as possible across the system architectures. We invite developers who have already faced this challenge in running across distinct present-day architectures to present their lessons learned and pest practices, and developers who are targeting the next generation HPC systems, such as those coming in the 2016-2018 time frame. How do we handle threads, vectorization, and memory hierarchies in as general a way as possible? Do we need to revise our data structures, when they may need to be different to map efficiently on different architectures?


The workshop will be structured as three segments

  1. Keynote presentation about experience developing a large-scale scientific application that is portable and performant across at least two architecturally distinct present-day super computer systems.
  2. A series of 20-minute contributed talks on topics including
    • Past experience porting large applications to multiple architectures
    • Development of libraries, frameworks, or programming approaches having portability across diverse HPC architectures as a goal
    • Forward looking plans to develop new or re-engineer existing large-scale scientific applications for future-generation HPC architectures. These might be from individual application teams or from larger efforts on a whole suite of applications.
    • Overviews of institutional programs/collaborations on portability and performance portability (representing, say, NSF or DOD centers)
    • Supercomputer vendor perspectives on portability
  3. A panel discussion, with questions from the audience, on the whole range of topics in the workshop.

Call For Participation:

The deadline for submissions closed on September 25, 2015.

If you would like to contribute a 20-minute talk to the workshop, please prepare and submit an extended abstract according to the instructions for authors.

Papers will be reviewed by three reviewers. Decisions on acceptance were sent to all authors on September 28, 2015.


Contact any of the organizers: